Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device in which the resistance of diffusion layers or diffusion layers and gate electrodes is reduced.
A complementary MOS semiconductor device, for example, a CMOS inverter, is by convention manufactured in the following way. To start, as shown in FIG. 1A, a P well region 31 of 5 .mu.m depth is formed in an N type, [100] silicon substrate 30. Then, element separation impurity layers 32 (impurity layers for preventing the formation of field inversion channels) are formed in the surface regions of the silicon substrate 30. Element separation oxide films 33 (field oxide films), are further formed on the impurity layers 32, respectively. Each paired impurity layer 32 and oxide film 33 serve as a separation region 34. Subsequently, as shown in FIG. 1B, a gate oxide film 35, 100 to 500.ANG. thick, is formed over each element forming region by a thermal oxidation process. An N type polysilicon layer is further deposited over the entire surface of the structure and patterned by photo engraving process (PEP) to form gate electrodes 36. Afterwards, an N type impurity, such as arsenic (As), is selectively ion-implanted into the structure, to form a source 37 and a drain 37 of an N channel MOSFET in the P well region 31, and a potential pick-up region 38 in the silicon substrate 30. Then, a P type impurity, such as boron (B), is selectively ion-implanted into the structure, to form a source 39 and a drain 39 of a P channel MOSFET in the silicon substrate 30, and a potential pick-up region 40 in the P type well region 31. Subsequently, as shown in FIG. 1C, a silicon oxide film 41 for interlayer insulation is deposited over the structure by a CVD (chemical vapor deposition) process, for example. Further, the formed silicon oxide film 41 is opened to form electrode lead-out portions, and wiring patterns 42 made of aluminum, for example, are formed thereon.
The above method for manufacturing a CMOS inverter is a general method for manufacturing complementary MOS semiconductor devices which has been widely employed. Polysilicon, for example, is used as the wiring material for the gate electrodes which allows the sources and the drains to be formed in a self-alignment manner by using a mask of the gate electrodes, and is also stable at high temperature when subjected to heat treatment. The polysilicon, however, has a property that, when it is doped with a high concentration of impurity, its resistivity is reduced by up to 10.sup.-3 ohm.multidot.cm. In a device based on microelements, this hinders any improvement of the operation speed.
Further, reduction of the sheet resistance of the source and the drain is up to 50 to 100 ohm/.quadrature.. In a case where the elements are extremely small and the on-resistance of the transistor is also small, the source and the drain have a large parasitic resistance. Therefore, it is impossible to increase the on-current.
To cope with this, recently, an approach has been proposed in which, to reduce wiring resistance, silicide layers are formed on the sources, drains, and gate electrodes. In this approach, after the sources, drains and gate electrodes are formed in the step of FIG. 1B, a metal film, such as a titanium film, is deposited over the structure. Then, heat treatment is applied to the structure through heat treatment, and the titanium reacts with silicon, to form a titanium silicide layer. The titanium which does not react with the silicon is etched away by chemical treatment. Finally, a titanium silicide of low resistance is formed on only the surfaces of the sources, drains and gate electrodes. This approach is called a salicide (self aligned silicide) method.
In a salicide process, silicides which result from the reaction of metal with silicon on the surfaces of the sources, drains and gate electrodes, grow and, in extreme cases, connect with each other. The silicides thus interconnected are left even after being subjected to the chemical etching process. Further, a natural oxide film exists in the interface between the metal and the silicon, which causes the reaction of the metal with the silicon to be nonuniform and possibly resulting in the source and/or the drain and the substrate to be shorted.